This  workshop will convene leading experts from academia, industry, and government to examine how low-dimensional (low-D) materials can transition from promising laboratory discoveries to industry-ready semiconductor technologies.

Low-D materials—including one-dimensional carbon nanotubes and two-dimensional semiconductors—have advanced rapidly in recent years. While research output and proof-of-concept demonstrations continue to grow, significant challenges remain in translating these materials into scalable, manufacturable semiconductor technologies.

Organized with support from the National Science Foundation (NSF) Directorate for Technology, Innovation and Partnerships (TIP) (Award #2549841), this workshop will bring together researchers and industry leaders to identify the key barriers slowing translation and to develop actionable strategies for overcoming them.

The discussions will inform a report that captures the current state of the field, outlines pathways to de-risking low-D semiconductor technologies, and provides recommendations on the investments, timelines, and collaborations needed to enable successful translation.

Why This Matters Now

Research on low-dimensional materials for microelectronics has reached a critical inflection point. While conventional semiconductor materials such as silicon face increasing performance limits at nanometer scales, low-D materials offer compelling advantages, including preserved carrier mobility at atomic thickness, compatibility with diverse substrates, and access to an exceptionally broad materials space.

At the same time, global competition in this area is intensifying, with a growing share of leading research activity occurring outside the United States. Without coordinated efforts to identify and overcome key translational barriers, the field risks remaining fragmented across individual laboratories, slowing progress and undermining long-term U.S. leadership.

This workshop comes at a moment when focused, collective action can have outsized impact - by aligning research priorities with industrial needs, clarifying benchmarks for success, and defining the steps required to move from promising demonstrations to scalable semiconductor technologies.

Goals of the Workshop

Participants will work together to:

• Build consensus on translation readiness - Assess whether low-dimensional semiconductor technologies are positioned for translation within the next ~6 years.
• Identify barriers to commercialization - Pinpoint key scientific, engineering, and manufacturing challenges preventing low-D semiconductors from moving from laboratory demonstrations to large-scale production.
• Develop strategies to overcome these barriers - Explore solutions across materials synthesis, fabrication processes, device architectures, metrology, and integration with existing semiconductor infrastructure.
• Define industry-relevant metrics - Identify the milestones that would give industry confidence to adopt low-D semiconductor technologies.
• Inform future directions - Provide insights to help shape possible future programs designed to support the translation of low-dimensional semiconductor technologies.

The workshop will be highly interactive, with facilitated discussions and small-group activities designed to draw on participant expertise and experience. A virtual collaboration hub and agenda will be shared closer to the workshop date.

Travel & Reimbursement Information

Lodging and travel expenses for non-local participants (more than 50 miles away) will be covered in accordance with U.S. government per diem guidelines. When you register, please indicate whether you will be requesting travel reimbursement, and we will follow up with additional details and next steps.